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MRF89XA
2.0 HARDWARE DESCRIPTION
The MRF89XA is an integrated, single chip, low-power
ISM band sub-GHz transceiver. A detailed block
diagram of the MRF89XA is illustrated in Figure 2-1 .
The frequency synthesizer is clocked by an external
12.8 MHz crystal, and frequency ranges from 863-870
MHz, 902-928 MHz and 950-960 MHz are possible.
The MRF89XA receiver employs a superheterodyne
architecture. The first IF is one-ninth of the RF
frequency (approximately 100 MHz). The second down
conversion, down converts the I and Q signals to
baseband in the case of the FSK receiver (zero-IF) and
to a low-IF (IF2) for the OOK receiver. After the second
down-conversion stage, the received signal is channel
select filtered and amplified to a level adequate for
demodulation. Both FSK and OOK demodulation are
available. Image rejection is achieved using a SAW
filter.
The baseband I and Q signals at the transmitter side are
digitally generated by a Direct Digital Synthesis (DDS)
whose Digital-to-Analog Converters (DAC) are followed
by two anti-aliasing low-pass filters that transform the
digital signal into analog In-Phase (I) and Quadrature
(Q) components with frequency as the selected
Frequency Deviation ( f dev ). The transmitter supports
both FSK and OOK modes of operation. The transmitter
has a typical output power of +12.5 dBm. An internal
transmit/receive switch combines the transmitter and
receiver circuits into a single-ended RFIO pin (pin 31).
The RFIO pin is connected through the impedance
matching circuitry to an external antenna. The device
operates in the low-voltage range of 2.1-3.6V, and in
Sleep mode, it operates at a very low-current state,
typically 0.1 μA.
The frequency synthesizer is based on an integer-N
PLL having PLL bandwidth of 15 kHz. Two
programmable frequency dividers in the feedback loop
of the PLL and one programmable divider on the
reference oscillator allow the LO frequency to be
adjusted. The reference frequency is generated by a
crystal oscillator running at 12.8 MHz.
The MRF89XA is controlled by a digital block that
includes registers to store the configuration settings of
the radio. These registers are accessed by a host
microcontroller through a Serial Peripheral Interface
(SPI). The quality of the data is validated using the
RSSI and bit synchronizer blocks built into the
transceiver. Data is buffered in a 64-byte transmitter or
receiver FIFO. The transceiver is controlled through a
4-wire SPI, interrupts (IRQ0 and IRQ1), PLOCK, DATA
and Chip Select pins for SPI are illustrated in
Figure 2-1 . On-chip regulators provide stable supply
voltages to sensitive blocks and allow the MRF89XA to
be used with supply voltages from 2.1-3.6V. Most
blocks are supplied with a voltage below 1.4V.
The MRF89XA supports the following feature blocks:
? Data filtering and whitening
? Bit synchronization
? 64-byte transmit/receive FIFO buffer
? General configuration registers
These features reduce the processing load, which
allows the use of simple, low-cost, 8-bit microcon-
trollers for data processing.
? 2010–2011 Microchip Technology Inc.
Preliminary
DS70622C-page 11
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